1. Field of the Invention
The present invention relates to a semiconductor memory device. For example, the invention relates to a semiconductor memory device which has FBCs (Floating Body Cells).
2. Related Art
In recent years, there is an FBC memory device as a semiconductor memory device expected as a memory replacing a 1T(Transistor)-1C (Capacitor) type DRAM. The FBC memory device has an FET (Field Effect Transistor) having a floating body (hereinafter, also “body”) formed on an SOI (Silicon On Insulator) substrate, and stores data “1” or data “0” depending on the number of majority carriers accumulated in this body.
As test items of the FBC memory, there are a static characteristic of a memory cell, a writing characteristic, a data retention characteristic, and a threshold voltage distribution. A test result of a memory cell formed in various process conditions is used to determine an optimum process condition and to analyze a defect cause. Many memory cells within a memory cell array need to be tested. To test the characteristics of these many memory cells, wirings for directly accessing the memory cells from an external pad via a DQ line are provided.
In the case of measuring a threshold voltage of a memory cell, for example, a change of a current flowing from the external pad to the memory cell is measured by controlling a gate voltage (word line voltage) of the memory cell. That is, a testing device directly applies a voltage to the memory cell through an external pad, without using a sense amplifier or a DQ buffer, thereby directly measuring the flowing current. The testing device changes the word line voltage from a low voltage to a high voltage. Further, the testing device uses as a threshold voltage the word line voltage when a predetermined current flows from the external pad to the memory cell. By repeatedly performing this to all memory cells, a distribution of the threshold voltage can be obtained.
However, usually because there is a variation in the threshold voltage of a memory cell, a current flowing from the external pad to the memory cell at a certain word line voltage is different for each bit. When the word line voltage is changed, a current flowing from the external pad to the memory cell also changes. Therefore, it has been difficult to simultaneously test all memory cells connected to a certain word line. Consequently, conventionally, the test needs to be executed to each bit. Accordingly, a long measuring time is necessary to test all the memory cells. Further, when the number of memory cells within the memory cell array increases, the test time becomes longer.